Bi-directional semiconductor switching devices are known in the art. Examples of two such prior art switching devices will be described with reference to the accompanying drawings in which:
FIG. 1 marked PRIOR ART is a sectional view of one known type of bi-directional protector device; and
FIG. 2 marked PRIOR ART is a sectional view of another known type of bi-directional protector device.
In U.S. Pat. No. 3,476,993 at FIG. 8, Aldrich et al show a five-layer two electrode semiconductor NPNPN switch. This Figure is substantially replicated in FIG. 1. The n-type regions 40, 41 at the top and bottom are diffused into respective p-type layers 42, 43, the diffusions and laterally adjacent exposed parts of the p-layers having common electrodes 45, 46 in conductive contact therewith. At a threshold voltage and current, the device switches, the polarity of the applied voltage being immaterial since the device is symmetrical.
As explained in the patent, when a negative voltage is applied to one of the electrodes 45 relative to the other electrodes 46, the pn junction bounding the adjacent n-type diffusion (e.g. base-emitter junction J.sub.E1) becomes forward biased and the junction between the central n-layer 44 and the intermediate p-layer 42 (e.g. base-collector junction J.sub.C1) becomes reverse-biased. At low voltage, the base-emitter junction is practically inoperative as an emitter because the n-type diffusion and the exposed part of the p-layer are shorted at the junction of the electrode 45. A small saturation current flows across the reverse-biased base-collector junction. As the voltage approaches the avalanche voltage of the base-collector junction, current flow across that junction tends to move along the p-layer 42 around the n-diffusion 40 towards that part of the electrode 45 adjacent the exposed p-region. The current increases rapidly and there is a resulting voltage drop produced by this current flow in that part of the p-layer next to the n-diffusion 40. This voltage drop acts to forward bias the base-emitter junction with the largest bias occurring at the edge of the junction furthest from the shorted contact point (i.e. furthest from the junction of J.sub.E1 and 45).
The effective emitter efficiency, and hence transistor gain, increases rapidly with increased current flow. When the current reaches a level I.sub.s referred to as the switching or turn-on current, at which the sum of the common base gains of the NPN (layers 40, 42, 44) and the central PNP (layers 42, 44, 43) transistor sections is greater than unity, the device switches on. As the voltage across the base-collector junction J.sub.C1 drops, the current originally distributed over the entire area of the p-layer shifts mainly to a region under the base-emitter junction J.sub.E1 and the device approaches its low impedance state. Thus a feedback action results in the switching transition being very abrupt.
The Aldrich device is rectangular in area with an overall length to width ratio of about 1:2. One n-diffusion is at the top of the device on one side, and the other n-diffusion is at the bottom of the device on a laterally and vertically opposed side. With this aspect ratio the n-type diffusions are essentially square (i.e. an aspect ratio of 1:1) in plan view, and do not effectively overlap. At high voltage, but before switching when current passes into the Aldrich device from the conductive electrode 46, at the exposed part of the p-region 43 on the lower side, it flows through the layers 44, 42 to the conductive electrode 45, and thus across and around the other n-type diffusion 40. After switching, the current flows straight upwardly from the conductive electrode 46 through the p-type input region 43 and the layers 44, 42 and the overlapping n-type diffusion 40 to the conductive electrode 45, with substantially uniform current density. The symmetrical action of the device is in fact achieved by two unidirectional devices sharing the same central n-type and intermediate p-type regions.
When an overvoltage condition of such device has terminated, it is required that the device switch itself off so that the circuit which the device protects can return to normal operation. Devices of the type shown in the Aldrich patent can be readily constructed to meet such requirements a fast turn-on times and low power dissipation, when the minimum holding current (i.e. the minimum current required to maintain conduction once the device has been triggered by an overvoltage) is small. Typical minimum holding currents would be in the order of 10 to 50 milliamps. This is not a problem in applications where all voltage across the device disappears once the overvoltage has been removed, such as in the Aldrich device which was initially developed as a switching device. However, in telephone applications, the protection device is generally connected to a telephone line having a central office battery supply voltage of typically up to 52 volts (nominally 48 volts) delivered through a 200 ohm resistor. As a result the minimum holding current for the device must be greater than 260 milliamps or else it will not return to its high impedance state once the overvoltage condition has disappeared.
It can be shown that the holding current I.sub.h is a function of alpha.sub.1, alpha.sub.2 and 1/R, where R is a measure of the effective resistive path in the p-layer of the active NPN device (i.e. the base layer) and alpha.sub.1 and alpha.sub.2 are the respective gains of the NPN and PNP transistors which make up the NPNP switching part of the device at one polarity. By decreasing the resistance R or the gains alpha.sub.1, alpha.sub.2 the value of the holding current I.sub.h can be increased. However, there is a penalty in decreasing the transistor gains since a device with low gain, usually as a result of reduced carrier lifetime, is very slow. This causes slow switching, very high power dissipation, and low device power handling capability. Alternatively, the value of R can be decreased by increased doping of the p-type layers and/or increased thickness of the p-type layers. However this decreases the gain alpha.sub.1 and hence is unsatisfactory.
An important aspect is the realization that the value of R increases in proportion to the width W of the n-type diffusion 40 since current crossing the collector junction J.sub.C1 must take a longer path through the p-layer 42 before it can flow to the top electrode 45 where that electrode meets the exposed p-type region. R also increases in inverse proportion to the length L (i.e. the length of the device perpendicular to the paper) of that diffusion 40. Thus R is approximately proportional to W/L, hence the holding current I.sub.h is proportional to L/W or an equivalent effective factor in the case of other than rectangular n-type diffusion geometry. For maximum power handling in either polarity the current density and hence the surface areas of the operating portions 40, 43 (or 41, 42 if the overvoltage current is reversed) of the device in contact with the conductive electrodes 45 and 46 should be about the same. As a result simply decreasing the width W of the n-type diffusion areas 40 and 41 also decreases the power handling capabilities of the device. These conflicting requirements do not appear to be reconcilable, utilizing the structure shown by Aldrich.
In U.S. Pat. No. 3,928,093 at FIG. 15, van Tongerloo et al show a circulo-symmetric NPNPN device in which the n-type diffusions 18 overlap one another. In this Figure which is substantially replicated in FIG. 2, the device is switched much as described previously for the Aldrich et al device. However, in this case, immediately prior to switching, current tends to flow directly between the exposed parts of the upper and lower p-regions 14, 14 in the PNP part of the device comprising layers 14, 10, 14. Unlike the Aldrich device, only a portion of the current flows through the offset part of the NPNP switching part. Consequently, the gain of the PNP device before switching is higher than in the Aldrich device and therefore the device can turn-on faster.
For the annular n-diffusion 18 used in the van Tongerloo device, W is approximately the difference between the outer R1 and inner R2 radii of the annular diffusion 18, and L is approximately the median circumference of this diffusion. The value of R can be reduced by reducing (R1-R2) and/or increasing L.
For a device having a fixed diameter the object of reducing the resistance of R by reducing the ratio of W/L (i.e. increasing L/W) and the object of having an n-diffusion 18 under the conductive contact equal in area to the exposed p-region 14 under that contact, are hard to reconcile. As stated above, this is a necessity for optimum power handling. Thus in the van Tongerloo device, if the requirement for a high L/W ratio is satisfied, then (R1-R2) is so small that the area of layer 14 remaining in the centre of the device is substantially larger than the area of the annular n-type diffusion 18. Conversely, if the two areas are equal, the L/W ratio will be about 18:1, in which case the resistance R is practically too high.
Thus to increase the holding current I.sub.h, the length to width ratio of the n-diffusion 18 can be altered to produce a very long narrow diffusion. However, the current carrying capacity of the resulting small area n-diffusion would be low, and the current output density would be extremely high in comparison to the input current density through the exposed p-diffusion 14 at the opposit face of the device. Consequently although the ratio of L/W is made higher than Aldrich it too cannot achieve a satisfactory minimum holding current while still meeting the other criteria.
It has been discovered that by modifying the topography of these bi-directional prior art devices and the surface area in contact with each conductive electrode in a particular way, it is possible to decrease the resistance R, while maintaining the total surface area of the electrodes in contact with each of the n-diffusions substantially equal to those of the p-regions. By making these modifications and concurrently maintaining the n-diffusions on opposite sides of the device in direct alignment with each other, the requirements for a protector having a high minimum holding current can be met without sacrificing the need for fast turn-on times and high current carrying capabilities during an overvoltage condition. As will be explained hereinafter, a key aspect of the modified topography is that the surface area be divided so that there is a significantly increased junction zone between the n-type diffusions, the p-type layers and the conductive electrodes. These modifications can be made to either a circulo-symmetric device as in van Tongerloo or a linear device as in Aldrich.
According to the present invention, there is provided a bi-directional overvoltage protection device comprising a central semiconductor layer of one semiconductor type, flanking semiconductor layers of an opposite semiconductor type, and at least two regions of said one semiconductor type in each of the flanking layers at each outer face thereof, each region being disposed directly opposite a region in the other flanking layer. Each of the outer faces having an electrode in conductive contact thereon which extends to cover the regions and exposed parts of the layers contiguous thereto. The device is characterized by a shorting junction formed at the intersection of the outer face of each layer, the electrode in conductive contact therewith and the contiguous region, the shorting junction extending along both sides of at least one of the regions. Consequently for a given width of that one region, its resistance when conducting is substantially one quarter that, were the electrode to contact the shorting junction along only one side. To have the same value of R in a device having a region shorted along only one side as in the prior art Figures, the width W would have to be decreased by a factor of four.
The device is also characterized by a topography in which the total area of the exposed parts of the layers is substantially equal to the total area of the regions at each surface so that when the device is conducting current in the on state, current input density at one surface is substantially equal to current output density at the opposed surface.
In one preferred device, the one semiconductor type is an n-type and the opposite semiconductor type is a p-type. In another, the device has a plurality of regions in each flanking layer, and the length to width of each of the regions is such that the resistance per unit length is substantially constant, whether or not the shorting junction at the intersection of the region, the layer and the contacting electrode is along one or both sides of the region.
A key aspect of this modified topography is the semiconductor regions in the flanking semiconductor layers of the device are disposed so that the conductive contact overlying the outer surfaces results in a shorting junction along both sides of the junction between the regions and the layers. For a given width of the region, this shorting junction along both sides quarters the effective resistance R over that which would be obtained were the junction shorted along only one side as taught in the prior art Aldrich and van Tongerloo patents. This occurs because the lateral distance between the shorting junction and the imaginary line of highest impedance midway between the two junctions is one half that of a region shorted on only one side thereby halving the impedance of each side. In addition, because both halves are in parallel, the resistance R is also halved so that the overall resistance is quartered. As a result it is now possible to provide a device having a sufficiently low resistance R that the minimum holding current requirements can be met, yet still meeting the requirement that the total areas be equal.
The protection device can be rectangular, having one or more parallel strip regions of length L and width W. Alternatively, the device can be circulo-symmetric having one or more concentric n-type regions formed in the p-type layer at each face. Each region having a radial width W and median circumference L. Preferably the effective aspect ratio L/W of all of the regions having a shorting junction along both sides is at least about 30:1.
The multilayer device chip may have mesa edges at which pn junctions between one of the n-diffusions and the adjacent p-layer intersects a surface of the mesa at an acute angle and said mesa surface has a passivating layer extending over it. A planar configuration may also be used. The device can alternatively be implemented as a PNPNP multilayer structure.